1. Field of the Invention
This invention relates to digital data apparatus of a character comprising a data processing unit and a plurality of peripheral units selectively addressable by the data processing unit for the transfer of digital data between the data processing unit and an addressed peripheral unit.
The invention relates more particularly to specific apparatus of the above character in which the data processing unit is a digitally operable processing unit and the peripheral units are random access memory units, although it will be apparent to one skilled in the art that the application of the invention to other forms of apparatus of the above character is possible.
2. Description of the Prior Art
Commonly, a (digitally operable) processing unit is implemented as an integrated circuit in a package, with connection to one or more (random access) memory units external to the integrated circuit package being effected by way of external connecting pins on the package. With such an implementation, it may be a requirement to accommodate connection between the processing unit and different numbers of memory units, according to particular uses of the apparatus.
However, in order to prevent any attempt by the processing unit to transfer data to a non-existent memory unit, it becomes necessary for the processing unit to detect which memory unit addresses are valid for selectively addressing memory units that are actually provided and which memory unit addresses are invalid because no memory units have been provided in respect to them.
A variety of arrangements for distinguishing between physically present and non-existent memory devices are already known in the art. In a first example, as described in U.K. patent specification No. 1,486,430, upper and lower address limits for each of a plurality of memory modules are automatically generated to maintain continuous address boundaries between the modules, even when the modules are replaced by modules of different storage capacities. Each address supplied by a processor over an address bus is compared in each module with the corresponding upper and lower limit addresses to produce an output when the address lies between the limits for that module, the output enabling the module's memory matrix. In a second example, as described in U.K. patent specification No. 1,468,783, a memory system in which the number and sizes of memory hardware modules are variable includes means for applying at least part of a word address to each module present, together with writable control means responsive to some of the bits of the address to apply to the module access-enabling signals generated as a function of these bits and of the current contents of the control means, module addressing thus being adjustable by varying the contents of the control means, e.g. according to module availability. In a third example, as described in European patent specification No. 0.028,312(A1) a data processing system has a non-volatile memory device adapted to contain data as to the availability of add-on read-only memories in the system, reference being made to this data during system operation. In a fourth example, as described in U.K. patent specification No. 1,430,486, a data processing system has a sectioned memory which is addressed from a memory address register to read out data to a data register. If an address does not correspond to a storage location in a memory section which is present in the system an output signal is generated from checking circuits. The checking circuits comprises in respect to each (notional) memory section, a logic circuit which is connected to receive a conditioning signal signifying the presence of the memory section concerned, when provided. At the start of a memory cycle of operation a command signal designates the memory section containing a storage location to be addressed. The appertaining logic circuit produces an output signal in response to the command signal, but only if it is also receiving the conditioning signal, to indicate that the storage location which is to be addressed is physically present.
It is an object of the present invention to provide improved and simpler means for distinguishing between physically present and nonexistent memory devices. By virtue of its simplicity, the invention affords particular advantage as applied to relatively small digital data apparatus employing microprocessors or minicomputers and variable size memory.